[aarch64-port-dev ] RFR: 8135231: add support for vectorizing double precision sqrt

[Edward Nevill]

On Wed, Sep 23, 2015 at 10:28 AM, Andrew Haley <aph at redhat.com> wrote:

> Hi,
>
> On 22/09/15 19:30, Edward Nevill wrote:
>
> > http://cr.openjdk.java.net/~enevill/8135231/webrev/
> >
> > JIRA issue: https://bugs.openjdk.java.net/browse/JDK-8135231
> >
> > This adds support for vector double sqrt for aarch64.
>
> This is an instance of the pattern "AdvSIMD two-reg misc".  Please use
> it.
>
> +  void fsqrt(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
> \
> +    starti;
>  \
> +    assert(T == T2S || T == T4S || T == T2D, "invalid arrangement");
> \
> +    f(0, 21), f((int)T & 1, 30), f(0b1011101, 29, 23);
> \
> +    f(T==T2D ? 1:0, 22), f(0b100001111110, 21, 10), rf(Vn, 5), rf(Vd, 0);
> \
> +  }
> +
>

 I have rewritten this as

+#define ASSERTION (T == T2S || T == T4S || T == T2D)
+  INSN(fsqrt, 1, 0b11111);
+#undef ASSERTION
+

New webrev

http://cr.openjdk.java.net/~enevill/8135231/webrev.02

Thanks for your help,

Ed.
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