RFR: 8150394: aarch64: add support for 8.1 LSE CAS instructions

[Andrew Haley]

On 22/02/16 20:32, Edward Nevill wrote:
> http://cr.openjdk.java.net/~enevill/8150394/webrev.0/
> 
> This adds support for the CAS instructions in armv8.1.

The C2 code for aarch64_enc_cmpxchg* is missing.

It's quite tricky to refactor to allow LSE instructions.  I'd add
a wordsize parameter to the cas instruction, like this:

#define INSN(NAME, a, r)                                                \
  void NAME(operand_size sz, Register Rs, Register Rt, Register Rn) {   \
    assert(Rs != Rn && Rs != Rt, "unpredictable instruction");          \
    compare_and_swap(Rs, Rt, Rn, sz, 1, a, r);                          \
  }
  INSN(cas, 0, 0)

And this gets rid of a ton of instruction definitions: we only need
CAS{A,L,AL}.

Pass the operand size down to MacroAssembler::cmpxchgw:

  enc_class aarch64_enc_cmpxchgw(memory mem, iRegINoSp oldval, iRegINoSp newval) %{
    MacroAssembler _masm(&cbuf);
    guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
    __ cmpxchg(Assembler::word, $mem$$base$$Register, $oldval$$Register,
               $newval$$Register,
               &Assembler::ldxrw, &MacroAssembler::cmpw, &Assembler::stlxrw);
  %}

void MacroAssembler::cmpxchgw(operand_size sz, Register oldv,
                              Register newv, Register addr, Register tmp,
			      Label &succeed, Label *fail) {

  if (UseLSE) {
    ...

It'll be necessary to pass a memory barrier flag too.

Andrew.