RFR: 8169901: AArch64: CompareAndExchange intrinsics clobber address register

[Roman Kennke]

the various compareAndExchange intrinsics in aarch64.ad potentially
clobber the address register:

;; cmpxchg {
          0x0000007f88b5919c: ldxr w0, [x0]
          0x0000007f88b591a0: cmp w0, w2
          0x0000007f88b591a4: b.ne 0x0000007f88b591b0
          0x0000007f88b591a8: stlxr w8, w3, [x0]
          0x0000007f88b591ac: cbnz w8, 0x0000007f88b5919c
         ;; } cmpxchg 

This is very bad because it's subsequently used (within the same
instruction) for the store-exclusive. It results in occasional
segfaults.

The fix is to declare the result register TEMP_DEF, this ensures that
it's distinct from address, newval and oldval. This also removes the
need to pin the input registers, which, I presume, was an attempt to
resolve this exact problem, but did not consider the address.

http://cr.openjdk.java.net/~rkennke/aarch64-cae/webrev.00/


bug: https://bugs.openjdk.java.net/browse/JDK-8169901

Tested by running jcstress (which segfaulted without this change).