RFR(S): 8194256 - AARCH64: SIMD shift instructions are incorrectly encoded

[Dmitrij Pochepko]

Hi all,

please review small patch for 8194256 - AARCH64: SIMD shift instructions 
are incorrectly encoded

I've noticed SIMD shift instructions wrong encoding when trying to use 
it. An intrinsic I was working on, generated incorrect assembly code 
with wrong shift value.

Existing code just copy "shift" bits into instruction bits(immh:immb), 
however, according to spec, it should be encoded as follows:


SIMD type <T>:

8B when immh = 0001 , Q = 0
16B when immh = 0001 , Q = 1
4H when immh = 001x , Q = 0
8H when immh = 001x , Q = 1
2S when immh = 01xx , Q = 0
4S when immh = 01xx , Q = 1
2D when immh = 1xxx , Q = 1


<shift> is encoded as follows:


for ushr and sshr:

(16-UInt(immh:immb)) when immh = 0001
(32-UInt(immh:immb)) when immh = 001x
(64-UInt(immh:immb)) when immh = 01xx
(128-UInt(immh:immb)) when immh = 1xxx


for shl:

(UInt(immh:immb)-8) when immh = 0001
(UInt(immh:immb)-16) when immh = 001x
(UInt(immh:immb)-32) when immh = 01xx
(UInt(immh:immb)-64) when immh = 1xxx


So, I've modified respective instruction generation code.


webrev: http://cr.openjdk.java.net/~dpochepk/8194256/webrev.01/

CR: https://bugs.openjdk.java.net/browse/JDK-8194256


I've checked this patch by generating intrinsic which use these 
instructions and verified assembly code.


Thanks,

Dmitrij