RFR(XS): 8165256: ARM64: vm/gc/concurrent/lp30yp10rp30mr0st300 Crash SIGBUS

[Andrew Haley]

On 15/02/17 13:06, Rickard Bäckman wrote:
> Adding both instruction cache invalidation of the interpreter stub when
> values are updated and a barrier between the stores of data/jump and the
> call.

I don't think the storestore fence does anything.  ICache::invalidate_range
should flush both caches to the point of unification.

Andrew.