RFR(S): 8204353 - AARCH64: optimize FPU load and stores in macroAssembler

[Dmitrij Pochepko]

Hi all,

please review small patch for 8204353 - AARCH64: optimize FPU load and 
stores in macroAssembler

This patch optimize fpu stores and loads by using ld1/st1 instructions 
which handle 4 registers instead of ldp/stp (2 registers). It makes 
respective code up to 2 times smaller. Thus it has more changes to be 
optimized in CPU.


Testing: I run hotspot jtreg compiler tests as sanity with patched and 
unpatched build. No new failures found.


CR: https://bugs.openjdk.java.net/browse/JDK-8204353

webrev: http://cr.openjdk.java.net/~dpochepk/8204353/webrev.01/


Thanks,

Dmitrij