RFR: 8210578: AArch64: Invalid encoding for fmlsvs instruction

[Andrew Dinn]

Can I please have a review for this trivial patch to correct the
encoding for fmlsvs.

JIRA Issue: https://bugs.openjdk.java.net/browse/JDK-8210578

Patch:

diff -r bbc7157ad9c5 src/hotspot/cpu/aarch64/assembler_aarch64.hpp
--- a/src/hotspot/cpu/aarch64/assembler_aarch64.hpp	Tue Sep 11 09:14:36
2018 +0200
+++ b/src/hotspot/cpu/aarch64/assembler_aarch64.hpp	Tue Sep 11 09:42:41
2018 +0100
@@ -2356,7 +2356,7 @@

   // FMLA/FMLS - Vector - Scalar
   INSN(fmlavs, 0, 0b0001);
-  INSN(fmlsvs, 0, 0b0001);
+  INSN(fmlsvs, 0, 0b0101);
   // FMULX - Vector - Scalar
   INSN(fmulxvs, 1, 0b1001);

The corrected bit identifies the sub_op which distinguishes a fused add
multiply vector by scalar (fmlavs) and add from a fused multiply vector
by scalar and subtract (fmlsvs).

Testing:
It appears that this instruction has never been exercised (by contrast,
fmlavs has -- by the power intrinsic I am currently reviewing). All I
have done to check this patch is ensure I can rebuild the JVM (there
isn't really any opportunity to test it until it is needed in an intrinsic).

Can I assume this is trivial enough to be pushed without running a
submit job?

regards,


Andrew Dinn
-----------
Senior Principal Software Engineer
Red Hat UK Ltd
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