RFR(S): 8210660: PPC64: Mapping floating point registers to vsx registers in ppc.ad

[Doerr, Martin]

Hi Michihiro,

I have added "RFR(S): 8210660" to the subject.

I don't think we need 2 nodes for ReplicateF with vector length 4. Both ones in your webrev are for Power8 so only one will be used.
Besides this, your change looks good to me.

Would you like to improve ReplicateD with vector length 2, too?

Thanks and best regards,
Martin


From: Michihiro Horie <HORIE at jp.ibm.com>
Sent: Mittwoch, 12. September 2018 18:11
To: hotspot-compiler-dev at openjdk.java.net
Cc: Doerr, Martin <martin.doerr at sap.com>; Gustavo Romero <gromero at linux.vnet.ibm.com>; Lindenmaier, Goetz <goetz.lindenmaier at sap.com>
Subject: RFR: PPC64: Mapping floating point registers to vsx registers in ppc.ad


Dear all,

Would you please review the following change?

Bug: https://bugs.openjdk.java.net/browse/JDK-8210660
Webrev: http://cr.openjdk.java.net/~mhorie/8210660/webrev.00/

In the current code emit for replicating the floating point value in ppc.ad, a floating point value is once stored in order to load as an integer value. However, when SuperwordUseVSX is enabled, this is redundant because the floating point registers are overlapped with vsx registers 0-31. We can use vsx instructions for replicating the floating point value by mapping the floating point register to the vsx register.


Best regards,
--
Michihiro,
IBM Research - Tokyo
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