RFR(S): 8210413: AArch64: Optimize div/rem by constant in C1

[Pengfei Li (Arm Technology China)]

Hi,

Could you please help review this optimization in C1 AArch64?

Currently, there are 2 LIR_Assembler::arithmetic_idiv() methods in c1_LIRAssembler_aarch64.cpp. One is left unimplemented, the other checks whether the divisor is a power-of-2 constant but does nothing optimized then. In this patch, I combined these 2 methods and added 2 below optimizations for integer div/rem.
1) Remove the div-by-zero check if the divisor is known to be a non-zero constant.
2) Use cheaper instructions instead of "sdiv" to do div/rem by a power-of-2 constant (including 1, 2, 4, 8, 16, ...)

JBS: https://bugs.openjdk.java.net/browse/JDK-8210413
webrev: http://cr.openjdk.java.net/~njian/8210413/webrev.00/

As Roman Kennke's original code comment said, using the temp register passed into arithmetic_idiv() is problematic. So I also use the rscratch1 directly for intermediate result in div/rem calculations. You could refer thread http://mail.openjdk.java.net/pipermail/aarch64-port-dev/2018-September/006315.html for this issue.

I've run jtreg full test with this patch and JVM option "-XX:TieredStopAtLevel=1" on an AArch64 server and no new issues found.

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Thanks,
Pengfei