RFR: 8223020: aarch64: expand minI_rReg and maxI_rReg patterns into separate instructions

[Yangfei (Felix)]

Hi,

    Please review:
    JBS: https://bugs.openjdk.java.net/browse/JDK-8223020
    Webrev: http://cr.openjdk.java.net/~fyang/8223020/webrev.00

    Currently, two instructions will be emitted for minI_rReg/maxI_rReg patterns: cmpw + cselw. 
    As these two instructions are always emitted together, the GCM (Global Code Motion) phase will 
    not be able to schedule them independently.  Patch expands minI_rReg and maxI_rReg patterns
    into separate instructions.  For the small test case on the JBS, GCM can do a better schedule with
    this change.  

    Jtreg tested with a fastdebug aarch64 build.  

    The test also reveals another issue: minI_rReg and maxI_rReg patterns are not taking advantage
    of the aarch64 zero register, so for maxI_rReg pattern we see code like this: 

    0x0000ffffa34148f0: mov w12, wzr        <======== 
    0x0000ffffa34148f4: cmp w10, w12        <======== 
    0x0000ffffa34148f8: csel w10, w10, w12, gt  <======== 

    which can be further simplified into:

    0x0000ffffa34148f4: cmp w10, wzr         <======== 
    0x0000ffffa34148f8: csel w10, w10, wzr, gt  <======== 

    But looks like it's hard to find a test case to trigger this issue for minI_rReg pattern. 
    I can fix this for maxI_rReg pattern with another patch if necessary. 

Thanks,
Felix