[aarch64-port-dev ] RFR: 8223020: aarch64: expand minI_rReg and maxI_rReg patterns into separate instructions

[Yangfei (Felix)]

Pushed.  Thanks for reviewing.  
A rough search shows more patterns which are possible candidates for expanding.  These were missed when I was doing a "size(8)" search.  
Some of these patterns use the reserved scratch registers when emitting code, which means we may use extra registers if we expand them in an elegant way.  
Should we expand them all?  Any suggestions?  


bytes_reverse_short

countTrailingZerosI
countTrailingZerosL

popCountI
popCountI_mem
popCountL
popCountL_mem

cmpL3_reg_reg
cmpL3_reg_imm

convI2B
convP2B

overflowMulI_reg
overflowMulI_reg_branch
overflowMulL_reg
overflowMulL_reg_branch

compF3_reg_reg
compD3_reg_reg
compF3_reg_immF0
compD3_reg_immD0
cmpLTMask_reg_reg
cmpLTMask_reg_zero

compareAndSwapB
compareAndSwapS
compareAndSwapI
compareAndSwapL
compareAndSwapP
compareAndSwapN

compareAndSwapBAcq
compareAndSwapSAcq
compareAndSwapIAcq
compareAndSwapLAcq
compareAndSwapPAcq
compareAndSwapNAcq

compareAndExchangeB
compareAndExchangeS

compareAndExchangeBAcq
compareAndExchangeSAcq

weakCompareAndSwapB
weakCompareAndSwapS
weakCompareAndSwapI
weakCompareAndSwapL
weakCompareAndSwapN
weakCompareAndSwapP
weakCompareAndSwapBAcq
weakCompareAndSwapSAcq
weakCompareAndSwapIAcq
weakCompareAndSwapLAcq
weakCompareAndSwapNAcq
weakCompareAndSwapPAcq

reduce_add2I
reduce_add4I
reduce_mul2I
reduce_mul4I
reduce_add2F
reduce_add4F
reduce_mul2F
reduce_mul4F
reduce_add2D
reduce_mul2D
reduce_max2F
reduce_max4F
reduce_max2D
reduce_min2F
reduce_min4F
reduce_min2D

vsra8B
vsra16B
vsrl8B
vsrl16B
vsra4S
vsra8S
vsrl4S
vsrl8S

vsra2I
vsra4I
vsrl2I
vsrl4I
vsra2L
vsrl2L

modI
modL

rolL_rReg
rolI_rReg

storePConditional
storeLConditional
storeIConditional

aarch64_enc_cmp_imm
aarch64_enc_cmpw_imm
aarch64_enc_cmp_imm_addsub
aarch64_enc_cmpw_imm_addsub


> 
> On 4/28/19 2:44 AM, Yangfei (Felix) wrote:
> 
> >     JBS: https://bugs.openjdk.java.net/browse/JDK-8223020
> >     Webrev: http://cr.openjdk.java.net/~fyang/8223020/webrev.00
> >
> >     Currently, two instructions will be emitted for minI_rReg/maxI_rReg
> patterns: cmpw + cselw.
> >     As these two instructions are always emitted together, the GCM (Global
> Code Motion) phase will
> >     not be able to schedule them independently.  Patch expands minI_rReg
> and maxI_rReg patterns
> >     into separate instructions.  For the small test case on the JBS, GCM can
> do a better schedule with
> >     this change.
> 
> OK.
> 
> I imagine that there are other patterns which might benefit from doing
> something similar.
> 
> I don't know if you are intending to do more of this kind of change,
> but if you are please group them together. It might be worth also
> producing a list beforehand and publishing that list here.