RFR(XXS): 8235288 :AVX 512 instructions inadvertently used on Xeon for small vector width operations
Viswanathan, Sandhya
sandhya.viswanathan at intel.com
Wed Dec 4 17:01:52 UTC 2019
Hi Vladimir,
Could you please sponsor this patch?
Best Regards,
Sandhya
-----Original Message-----
From: Vladimir Kozlov <vladimir.kozlov at oracle.com>
Sent: Tuesday, December 03, 2019 2:41 PM
To: Viswanathan, Sandhya <sandhya.viswanathan at intel.com>
Cc: hotspot compiler <hotspot-compiler-dev at openjdk.java.net>
Subject: Re: RFR(XXS): 8235288 :AVX 512 instructions inadvertently used on Xeon for small vector width operations
Looks good.
Thanks
Vladimir
> On Dec 3, 2019, at 1:33 PM, Viswanathan, Sandhya <sandhya.viswanathan at intel.com> wrote:
>
> For vector replicate and reduction operations vinsert and vextract instructions are used.
> When UseAVX level is set to 3, these instructions are unnecessarily encoded with 512-bit vector width.
> Only for KNL platform which doesn't support AVX512 variable length encoding, the 512-bit wide instruction need to be used.
> All other Xeon platforms should use the appropriate 256-bit wide vector instruction.
>
> JBS: https://bugs.openjdk.java.net/browse/JDK-8235288
> Webrev: http://cr.openjdk.java.net/~sviswanathan/8235288/webrev.00/
>
> Please review and approve.
>
> Best Regards,
> Sandhya
>
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