[14] RFR (XS): 8234392: C2: Extend Matcher::match_rule_supported_vector() with element type information

John Rose john.r.rose at oracle.com
Tue Dec 10 20:34:39 UTC 2019


On Dec 10, 2019, at 12:03 PM, Vladimir Ivanov <vladimir.x.ivanov at oracle.com> wrote:
> 
>> This is probably an oversimplification, so file it as BS (brain storming).
>> If such a consolidation of sizing logic is possible, it can be done as
>> a separate cleanup.
> 
> Unfortunately, single- and double-precision FP operations are scattered between AVX512F and AVX512DQ, so I doubt it makes sense to limit FP operations to 256-bit vectors when AVX512DQ is not available.
> 
> It would severely penalize Xeon Phis (which lack BW, DQ, and VL extensions), but maybe there'll be a moment when Skylake (F+CD+BW+DQ+VL) can be chosen as the baseline.

Yeah, I saw that coming after I visited the trusty intrinsics guide
https://software.intel.com/sites/landingpage/IntrinsicsGuide/
> 
> Anyway, I got your idea and it makes perfect sense to me to collect such ideas.

Thanks!  Next review, please… 




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