[14] RFR (L): 8235719: C2: Merge AD instructions for ShiftV, AbsV, and NegV nodes

[John Rose]

Thank you, reviewed.

For consistency, I’d expect to see the AD file mention vshiftq
instead of in or in addition to the very specific evpsraq.
Maybe actually call vshiftq (consistent with other parts of
AD) and comment that it calls evpsraq?  I had to look inside the
macro assembler to verify that evpsraq was properly aligned
with the other cases.  Or just leave a comment saying this is
what vshiftq would do also, like the other instructions.

For vabsnegF, I suggest adding a comment here:

+  predicate(n->as_Vector()->length() == 2 ||
+            // case 4 is handled as a 1-operand instruction by vabsneg4F
+            n->as_Vector()->length() == 8 ||
+            n->as_Vector()->length() == 16);

— Commentator John

On Dec 10, 2019, at 2:29 PM, Vladimir Ivanov <vladimir.x.ivanov at oracle.com> wrote:
> 
> http://cr.openjdk.java.net/~vlivanov/jbhateja/8235719/webrev.00/all
> https://bugs.openjdk.java.net/browse/JDK-8235719
> 
> Merge AD instructions for the following vector nodes:
>  - LShiftV*, RShiftV*, URShiftV*
>  - AbsV*
>  - NegV*
> 
> Individual patches:
> http://cr.openjdk.java.net/~vlivanov/jbhateja/8235719/webrev.00/individual
> 
> As Jatin described, merging is applied only to AD instructions of similar shape. There are some more opportunities for reduction/merging left, but they are deliberately left out for future work.
> 
> The patch is derived from the initial version of generic vector support [1]. Generic vector support was reviewed earlier [2].
> 
> Testing: tier1-4, test run on different CPU flavors (KNL, SKL, etc)
> 
> Contributed-by: Jatin Bhateja <jatin.bhateja at intel.com>
> Reviewed-by: vlivanov, sviswanathan, ?
> 
> Best regards,
> Vladimir Ivanov
> 
> [1] https://mail.openjdk.java.net/pipermail/hotspot-compiler-dev/2019-August/034822.html
> 
> [2] https://mail.openjdk.java.net/pipermail/hotspot-compiler-dev/2019-November/036016.html