RFR(M):8167065: Add intrinsic support for double precision shifting on x86_64

[Kamath, Smita]

Hi,


As per Intel Architecture Instruction Set Reference [1] VBMI2 Operations will be supported in future Intel ISA. I would like to contribute optimizations for BigInteger shift operations using AVX512+VBMI2 instructions. This optimization is for x86_64 architecture enabled.

Link to Bug: https://bugs.openjdk.java.net/browse/JDK-8167065

Link to webrev : http://cr.openjdk.java.net/~svkamath/bigIntegerShift/webrev00/



I ran jtreg test suite with the algorithm on Intel SDE [2] to confirm that encoding and semantics are correctly implemented.


[1] https://software.intel.com/sites/default/files/managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf (vpshrdv -> Vol. 2C 5-477 and vpshldv -> Vol. 2C 5-471)

[2] https://software.intel.com/en-us/articles/intel-software-development-emulator


Regards,

Smita Kamath