[14] RFR(XXS):8236364:TEMP vector registers could be incorrectly assigned upper bank xmm registers after Generic Operands (JDK-8234391)

[Vladimir Ivanov]

Hi Sandhya,

> Webrev: http://cr.openjdk.java.net/~sviswanathan/8236364/webrev.00/

I'd prefer to see the check as a special case with a comment:

  MachOper* Matcher::specialize_generic_vector_operand(MachOper* 
generic_opnd, uint ideal_reg) {
    assert(Matcher::is_generic_vector(generic_opnd), "not generic");
    bool legacy = (generic_opnd->opcode() == LEGVEC);
+  if (!VM_Version::supports_avx512vlbwdq() && // KNL
+      is_temp && !legacy && (ideal_reg == Op_VecZ)) {
+    // Conservatively specialize 512bit vec TEMP operands to legVecZ 
(zmm0-15) on KNL.
+    return new legVecZOper();
+  }
    if (legacy) {
      switch (ideal_reg) {
        case Op_VecS: return new legVecSOper();

Otherwise, looks good.

I consider it as a stop-the-gap solution for 14. In 15 we need to get 
rid of it and adjust TEMP operand types in x86.ad instead. Please, file 
an RFE for it.

Best regards,
Vladimir Ivanov

> 
> Best Regards,
> Sandhya
> 
> 
>