RFR: 8227222 : vmTestbase/jit/FloatingPoint/gen_math/Loops04/Loops04.java hits assert

[Bhateja, Jatin]

Hi Tobias,

With targets which do not support AVX512VL feature strict EVEX encoding is imposed in following cases:-
  1) Vector length of its operand is 512 bits.
  2) Instruction is newly added one for AVX512* target.

RA is target agnostic and only way it constrains allocation of an operand is by looking at its register masks (associated with Register classes). 

During assembling we do perform EVEX to VEX transformations but this is post allocation.

Thus for an instruction even if its VEX equivalent exists but if its operand got allocated from higher-register bank(16-31) EVEX-to-VEX transformation will not be possible. 
Now, for AVX512 target which does not have AVX512VL feature but need to access lower vector lengths (which was the scenario in this case) only way to get through is to 
read 512 bits for vector operands which may hit the performance[1].

Keeping in view above points, changing the register class of instruction patterns looked good option. Please suggest.

Best Regards,
Jatin

[1] Section 17.26 : https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-optimization-reference-manual


> -----Original Message-----
> From: Tobias Hartmann [mailto:tobias.hartmann at oracle.com]
> Sent: Tuesday, July 9, 2019 11:54 AM
> To: Bhateja, Jatin <jatin.bhateja at intel.com>; hotspot-compiler-
> dev at openjdk.java.net
> Subject: Re: RFR: 8227222 :
> vmTestbase/jit/FloatingPoint/gen_math/Loops04/Loops04.java hits assert
> 
> Hi Jatin,
> 
> On 09.07.19 05:54, Bhateja, Jatin wrote:
> > RA constraints the allocation set of an operand by using the register masks
> associated with operand's register classes. Thus using legacy register classes
> in the instruction patterns for reduction case will guide allocator to assign
> register from lower register bank (0-15).
> 
> But doesn't that mean that we don't use all available registers on a system
> with AVX512VL support?
> 
> Best regards,
> Tobias