RFR(S) JDK-8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions

[Vladimir Kozlov]

Hi Smita,

You don't need #ifdef _LP64 in stubGenerator_x86_64.cpp. This file is compiled only for 64-bit JVM.
You also have trailing spaces - please remove them.

Changes seem fine otherwise. I submit tier1 testing to make sure it builds.

Thanks,
Vladimir

On 11/7/19 12:12 PM, Kamath, Smita wrote:
> Hi Vladimir,
> 
> 
> As per Intel Architecture Instruction Set Reference [1] Vector AES (VAES) Operations will be supported in future Intel ISA. I would like to contribute an optimization for AES-CTR algorithm using AVX512+VAES instructions. This optimization is for x86_64 architecture that have AVX512-VAES enabled. I ran jtreg test suite with the algorithm on Intel SDE [2] to confirm that encoding and semantics are correctly implemented.
> 
> 
> I, smita.kamath at intel.com<mailto:smita.kamath at intel.com> , Regev Shemy (regev.shemy at intel.com<mailto:regev.shemy at intel.com>) and Shay Gueron, (shay.gueron at intel.com<mailto:shay.gueron at intel.com>) are contributors to this code.
> 
> Link to Bug: https://bugs.openjdk.java.net/browse/JDK-8233741
> 
> Link to webrev: https://cr.openjdk.java.net/~srukmannagar/AESCTR/webrev.01
> 
> 
> [1] https://software.intel.com/sites/default/files/managed/ad/01/253666-sdm-vol-2a.pdf  (Pages 156 - 159)
> 
> [2] https://software.intel.com/en-us/articles/intel-software-development-emulator
> 
> 
> Regards,
> Smita Kamath
>