RFR: 8234160: ZGC: Enable optimized mitigation for Intel jcc erratum in C2 load barrier

[Per Liden]

On 11/19/19 3:20 PM, erik.osterlund at oracle.com wrote:
> Hi,
> 
> Intel released an erratum (SKX102) which causes "unexpected system 
> behaviour" when branches
> (including fused conditional branches) cross or end at 64 byte boundaries.
> They are mitigating this by rolling out microcode updates that disable 
> micro op caching for
> conditional branches that cross or end at 32 byte boundaries. The 
> mitigation can cause
> performance regressions, unless affected branches are aligned properly.
> 
> The erratum and its mitigation are described in more detail in this 
> document published by Intel:
> https://www.intel.com/content/dam/support/us/en/documents/processors/mitigations-jump-conditional-code-erratum.pdf 
> 
> 
> My intention for this patch is to introduce the infrastructure to 
> determine that we may
> have an affected CPU, and mitigate this by aligning the most important 
> branch in the whole
> JVM: the ZGC load barrier fast path check. Perhaps similar methodology 
> can be reused later
> to solve this for other performance critical code, but that is outside 
> the scope of this CR.
> 
> The sprinkling of nops do not seem to cause regressions in workloads I 
> have tried, given a
> machine without the JCC mitigations.
> 
> Bug:
> https://bugs.openjdk.java.net/browse/JDK-8234160
> 
> Webrev:
> http://cr.openjdk.java.net/~eosterlund/8234160/webrev.00/

Looks good!

I think this is a good solution for ZGC for now. Solving this for all 
non-ZGC branches is a lot more involved. But if/when a more generic 
solution arrives, we can easily just remove this again.

/Per

> 
> Thanks,
> /Erik