RFR: 8230565: ZGC: Redesign C2 load barrier to expand on the MachNode level

[Andrew Haley]

On 10/8/19 2:37 PM, Nils Eliasson wrote:
> For the non-Aarch64 parts: Looks good!

+int MacroAssembler::pop_fp(unsigned int bitset, Register stack) {
+  int words_pushed = 0;
+
+  // Scan bitset to accumulate register pairs
+  unsigned char regs[32];
+  int count = 0;
+  for (int reg = 0; reg <= 31; reg++) {
+    if (1 & bitset)
+      regs[count++] = reg;
+    bitset >>= 1;
+  }
+  regs[count++] = zr->encoding_nocheck();

This use of ZR looks wrong in FP code. There is no floating-point ZR.

-- 
Andrew Haley  (he/him)
Java Platform Lead Engineer
Red Hat UK Ltd. <https://www.redhat.com>
https://keybase.io/andrewhaley
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