RFR: 8230565: ZGC: Redesign C2 load barrier to expand on the MachNode level

[Per Liden]

Hi,

On 10/11/19 10:15 AM, Nils Eliasson wrote:
> 
> On 2019-10-10 20:57, Andrew Haley wrote:
>> On 10/8/19 2:37 PM, Nils Eliasson wrote:
>>> For the non-Aarch64 parts: Looks good!
>> +int MacroAssembler::pop_fp(unsigned int bitset, Register stack) {
>> +  int words_pushed = 0;
>> +
>> +  // Scan bitset to accumulate register pairs
>> +  unsigned char regs[32];
>> +  int count = 0;
>> +  for (int reg = 0; reg <= 31; reg++) {
>> +    if (1 & bitset)
>> +      regs[count++] = reg;
>> +    bitset >>= 1;
>> +  }
>> +  regs[count++] = zr->encoding_nocheck();
>>
>> This use of ZR looks wrong in FP code. There is no floating-point ZR.
>>
> Right. We shouldn't use zr here - but any register will do since its 
> just padding to get an even count of spills.
> 
> -  regs[count++] = zr->encoding_nocheck();
> 
> + regs[count++] = 0; // Add reg 0 as padding - we want to spill an even 
> number of registers
> 
> // Nils
> 

Nils, will you file a bug and fix this?

cheers,
Per