add microcode version to the hs_err files
Ivanov, Vladimir A
vladimir.a.ivanov at intel.com
Fri Jul 17 19:57:42 UTC 2020
Hello,
could you please review the patch http://cr.openjdk.java.net/~sviswanathan/Vladimir/8249672/webrev.00/
This patch add the microcode version for different OSes that may be useful in the issue resolution process.
The reported microcode version for different OSes loos as:
Linux (RHEL7.7):
# cat hs_err_pid251046.log |grep microc
CPU: total 112 (initial active 112) (28 cores per cpu, 2 threads per core) family 6 model 85 stepping 4 microcode 0x200005e, cmov, cx8, fxsr, mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, popcnt, vzeroupper, avx, avx2, aes, clmul, erms, rtm, 3dnowpref, lzcnt, ht, tsc, tscinvbit, bmi1, bmi2, adx, fma, clflush, clflushopt, clwb
Windows (Win10, v1809):
CPU: total 4 (initial active 4) (2 cores per cpu, 2 threads per core) family 6 model 142 stepping 9 microcode 0xb4, cmov, cx8, fxsr, mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, popcnt, vzeroupper, avx, avx2, aes, clmul, erms, rtm, 3dnowpref, lzcnt, ht, tsc, tscinvbit, bmi1, bmi2, adx, fma, clflush, clflushopt
MacOS (Darwin):
$ cat hs_err_pid95187.log |grep microc
CPU: total 8 (initial active 8) (4 cores per cpu, 2 threads per core) family 6 model 126 stepping 5 microcode 0x78, cmov, cx8, fxsr, mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, popcnt, vzeroupper, avx, avx2, aes, clmul, erms, 3dnowpref, lzcnt, ht, tsc, tscinvbit, bmi1, bmi2, adx, sha, fma, clflush, clflushopt
Thanks, Vladimir
Thanks, Vladimir
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