[15] RFR(S): 8240905: assert(mem == (Node*)1 || mem == mem2) failed: multiple Memories being matched at once?

[Tobias Hartmann]

Hi Vladimir,

thanks for the review!

On 20.03.20 21:22, Vladimir Kozlov wrote:
>> Since JDK-8031321 which added support for Intel's bit manipulation instructions to JDK 8u20, we have
>> rules in the .ad file that are matching two LoadNodes and therefore two memory inputs to a single
>> instruction (for example, blsiI_rReg_mem [1]). As of today, these BMI1 instructions are still the
>> only ones that match multiple memory.
> 
> Correction: multiple *uses* of a memory input.

Right.

> I thought we can't have 2 memory inputs in mach instructions but to my surprise I found 3 cases in
> x86_32.ad. But they are exceptions - they handle FPU instructions: addFPR24_mem_*,
> mulFPR24_mem_mem.  There are few other in x86_32.ad which moves data between memory and stackSlot.
> But I don't see anything like that in x86_64.ad or other architectures .ad files.

Yes and these are not affected by my patch.

> I agree with this solution. We will fallback to Register version of instructions for such cases.

Thanks, I'm currently running some performance benchmarks for sanity.

> And someone have to test 32-bit build with these changes.

Any volunteers? :)

Best regards,
Tobias