RFR: 8267356: AArch64: Vector API SVE codegen support [v4]

[Andrew Haley]

On Thu, 29 Jul 2021 08:21:54 GMT, Ningsheng Jian <njian at openjdk.org> wrote:

>> This is the integration of current SVE work done in panama-vector/vectorIntrinscs, which includes:
>> 
>> 1. Code generation for Vector API c2 IR nodes with SVE.
>> 2. Non-max vector size support with SVE, e.g. using *128Vector (and *64Vector) APIs on 256-bit SVE environment could also generate optimized SVE instructions with predicate feature.
>> 3. Some more SVE assemblers (and tests) used by the codegen part.
>> 
>> Note: VectorMask<E\> is still represented in vector register, a further improvement to map mask to predicate register is under development at https://github.com/openjdk/panama-vector/tree/vectorIntrinsics+mask
>> 
>> 
>> Test: tier1-3 with vector api test cases passed on 512-bit SVE hardware with MaxVectorSize=16/32/64.
>
> Ningsheng Jian has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Add missing part

src/hotspot/cpu/aarch64/assembler_aarch64.cpp line 70:

> 68: 
> 69: Assembler::SIMD_Arrangement Assembler::esize2arrangement(unsigned esize, bool isQ) {
> 70:   assert(esize < ARRAY_SIZE(_esize2arrangement_table) &&

Please consider making this a guarantee. The cost is minimal, and we've been saved by guarantees elsewhere in this file.

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PR: https://git.openjdk.java.net/jdk/pull/4122