RFR: 8267356: AArch64: Vector API SVE codegen support [v4]

[Andrew Haley]

On Thu, 29 Jul 2021 08:21:54 GMT, Ningsheng Jian <njian at openjdk.org> wrote:

>> This is the integration of current SVE work done in panama-vector/vectorIntrinscs, which includes:
>> 
>> 1. Code generation for Vector API c2 IR nodes with SVE.
>> 2. Non-max vector size support with SVE, e.g. using *128Vector (and *64Vector) APIs on 256-bit SVE environment could also generate optimized SVE instructions with predicate feature.
>> 3. Some more SVE assemblers (and tests) used by the codegen part.
>> 
>> Note: VectorMask<E\> is still represented in vector register, a further improvement to map mask to predicate register is under development at https://github.com/openjdk/panama-vector/tree/vectorIntrinsics+mask
>> 
>> 
>> Test: tier1-3 with vector api test cases passed on 512-bit SVE hardware with MaxVectorSize=16/32/64.
>
> Ningsheng Jian has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Add missing part

src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.cpp line 957:

> 955:     case BoolTest::eq: condition = Assembler::EQ; break;
> 956:     case BoolTest::ne: condition = Assembler::NE; break;
> 957:     case BoolTest::le: z1 = zm; z2 = zn;  // Swap the two inputs

This might warn on some targets, so we'd need to fix it anyway, so please do it now. Better to duplicate the action and break.

-------------

PR: https://git.openjdk.java.net/jdk/pull/4122