RFR: 8261142: AArch64: Incorrect instruction encoding when right-shifting vectors with shift amount equals to the element width [v6]

[Dong Bo]

> In vectorAPI, when right-shifting a vector with a shift equals to the element width, the shift is transformed to zero,
> see `src/jdk.incubator.vector/share/classes/jdk/incubator/vector/VectorOperators.java`:
>     /** Produce {@code a>>>(n&(ESIZE*8-1))}. Integral only. */
>     public static final /*bitwise*/ Binary LSHR = binary("LSHR", ">>>", VectorSupport.VECTOR_OP_URSHIFT, VO_SHIFT);
> 
> The aarch64 assembler generates wrong or illegal instructions in this case, e.g. for the JAVA code below on aarch64,
> assembler call `__ ushr(dst, __ T8B, src, 0)`, the instruction generated is not `ushr dst.8B, src.8B, 0`, but `ushr dst.4H, src.4H, 16` instead.
> According to local tests, JVM gives wrong results for byte/short and crashes with SIGILL for integer/long.
> ByteVector vba = ByteVector.fromArray(byte64SPECIES, bytesA, 8 * i);
> vbb.lanewise(VectorOperators.ASHR, 8).intoArray(arrBytes, 8 * i);
> 
> The legal right shift amount should be in the range 1 to the element width in bits on aarch64:
> https://developer.arm.com/documentation/dui0801/f/A64-SIMD-Vector-Instructions/USHR--vector-?lang=en
> 
> This fix handles zero shift separately. If the shift is zero, it generates `orr` for right shift, `addv` for right shift and accumulate.
> Verified with linux-aarch64-server-fastdebug, tier1. Also created a jtreg to reproduce the issue and for regression tests.

Dong Bo has updated the pull request with a new target base due to a merge or a rebase. The incremental webrev excludes the unrelated changes brought in by the merge/rebase. The pull request contains six additional commits since the last revision:

 - add tests in aarch64-asmtest.py
 - fix windows operator precedence error and cleanup testcase
 - Merge branch 'master' into aarch64_vector_api_shift
 - fix windows build failure
 - generate add if shift == 0 for accumulation and fix some test code
 - back out AD modifications and handle zero shift in assembler

-------------

Changes:
  - all: https://git.openjdk.java.net/jdk/pull/2472/files
  - new: https://git.openjdk.java.net/jdk/pull/2472/files/d75ee99e..d746f209

Webrevs:
 - full: https://webrevs.openjdk.java.net/?repo=jdk&pr=2472&range=05
 - incr: https://webrevs.openjdk.java.net/?repo=jdk&pr=2472&range=04-05

  Stats: 22519 lines in 709 files changed: 13758 ins; 4768 del; 3993 mod
  Patch: https://git.openjdk.java.net/jdk/pull/2472.diff
  Fetch: git fetch https://git.openjdk.java.net/jdk pull/2472/head:pull/2472

PR: https://git.openjdk.java.net/jdk/pull/2472