RFR: 8261142: AArch64: Incorrect instruction encoding when right-shifting vectors with shift amount equals to the element width [v6]

[Dong Bo]

On Thu, 18 Feb 2021 09:35:07 GMT, Andrew Haley <aph at openjdk.org> wrote:

>> Dong Bo has updated the pull request with a new target base due to a merge or a rebase. The incremental webrev excludes the unrelated changes brought in by the merge/rebase.
>
> src/hotspot/cpu/aarch64/assembler_aarch64.hpp line 2694:
> 
>> 2692:     assert((1 << ((T>>1)+3)) > shift, "Invalid Shift value");           \
>> 2693:     if (shift == 0) {                                                   \
>> 2694:       bool accumulate = ((opc2 & 0b100) != 0);                          \
> 
> Is this correct, according to the definition in the Architecture Reference Manual? It doesn't look like it to me. Assembler methods should generate bit patterns exactly as defined in the Manual. This logic should be in a MacroAssembler method.

Hi, I moved the logic into MacroAssembler.
The assert is kept to make sure that we would never pass a zero right shift to assemlber.

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PR: https://git.openjdk.java.net/jdk/pull/2472