RFR: 8261142: AArch64: Incorrect instruction encoding when right-shifting vectors with shift amount equals to the element width [v7]

[Dong Bo]

On Fri, 19 Feb 2021 14:42:15 GMT, Andrew Haley <aph at openjdk.org> wrote:

>> Dong Bo has refreshed the contents of this pull request, and previous commits have been removed. The incremental views will show differences compared to the previous content of the PR.
>
> src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp line 554:
> 
>> 552: 
>> 553:   WRAP(usra) WRAP(ssra)
>> 554: #undef WRAP
> 
> Are ssra and usra tested by anything? I don't seem them accessed in the test case.

Updated. The `ssra/usra` are accessed by tests in `TestVectorShiftImmAndAccumulate.java`.
Manually injected error by changing `addv` to `subv` if shifting right and accumulating with 0, the tests failed as expected.

The `vba.add(vbb.lanewise(SHIFT, Imm))` pattern in `TestVectorShiftImmAndAccumulate.java` are actually the same with the original code in `TestVectorShiftImm.java`.
As of now, I have no idea why `ssra/usra` are not accessed by the previous test code.
The `vba.add(vbb.lanewise(SHIFT, Imm))` pattern should match `ssra/usra` anyway.
I think we need a separate investigation.

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PR: https://git.openjdk.java.net/jdk/pull/2472