RFR: 8269878: Handle redundant reg-2-reg moves in X86 backend

[Vladimir Kozlov]

On Tue, 6 Jul 2021 17:04:28 GMT, Jatin Bhateja <jbhateja at openjdk.org> wrote:

> Chain patterns which connects various legacy, VL and non-legacy USE - DEF operands during selection need not emit a reg-2-reg move instruction. C2 register allocator can handle these cases by back propagating the register mask from USE to DEF e.g.
> 
> USE (regD) <- DEF( legRegD) : Not an issue since regD can accommodate ranges allocated to legRegD.
> 
> USE (legRegD) <- USE (regD) : Not an issue since Allocator will back propagate legRegD mask from USE to its DEF node, which will constrain the allocation set to lower register bank.
> 
> Same logic applies to vlRegD , rRegD, legRegD combinations.
> 
> These machine nodes are redundant post selection and can be removed during generic operand resolution phase.

Other than comments it looks good to me.
I will test it.

src/hotspot/cpu/x86/x86_32.ad line 5024:

> 5022: //               in the encode section of the architecture description.
> 5023: 
> 5024: // Chain instructions needed by selection algorithm.

Please update comment similar to `MoveVec2Leg` instruction:

// Dummy reg-to-reg vector moves. Removed during post-selection cleanup.

src/hotspot/cpu/x86/x86_64.ad line 4823:

> 4821: //               in the encode section of the architecture description.
> 4822: 
> 4823: // Chain instructions needed by selection algorithm.

Fix comment.

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PR: https://git.openjdk.java.net/jdk/pull/4693