RFR: 8267356: AArch64: Vector API SVE codegen support [v2]

[Ningsheng Jian]

On Mon, 26 Jul 2021 08:34:42 GMT, Andrew Haley <aph at openjdk.org> wrote:

>> Ningsheng Jian has updated the pull request with a new target base due to a merge or a rebase. The pull request now contains one commit:
>> 
>>   8267356: AArch64: Vector API SVE codegen support
>>   
>>   This is the integration of current SVE work done in
>>   panama-vector/vectorIntrinscs, which includes:
>>   
>>   1. Code generation for Vector API c2 IR nodes with SVE.
>>   2. Non-max vector size support with SVE, e.g. using *128Vector APIs on
>>      256-bit SVE environment could also generate optimized SVE
>>      instructions with predicate feature.
>>   3. Some more SVE assemblers (and tests) used by the codegen part.
>>   
>>   Note: VectorMask<E> is still represented in vector register, a further
>>   improvement to map mask to predicate register is under development at
>>   https://github.com/openjdk/panama-vector/tree/vectorIntrinsics+mask
>>   
>>   Test: tier1-3 with vector api test cases passed on 512-bit SVE hardware
>>   with MaxVectorSize=16/32/64.
>
> src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.cpp line 953:
> 
>> 951:   if (bt == T_FLOAT || bt == T_DOUBLE) {
>> 952:     switch (cond) {
>> 953:       case BoolTest::eq: sve_fcmeq(pd, size, pg, zn, zm); break;
> 
> Wouldn't this work better by making cond and size arguments to sve_fcm ?

Thanks! But we still need to map c2 specific condition value in BoolTest to instruction condition encoding. So, I think making cond arguments to fcm doesn't make help here. (This also aligns current NEON implementation.) What do you think?

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PR: https://git.openjdk.java.net/jdk/pull/4122