RFR: 8267356: AArch64: Vector API SVE codegen support [v4]

[Ningsheng Jian]

> This is the integration of current SVE work done in panama-vector/vectorIntrinscs, which includes:
> 
> 1. Code generation for Vector API c2 IR nodes with SVE.
> 2. Non-max vector size support with SVE, e.g. using *128Vector (and *64Vector) APIs on 256-bit SVE environment could also generate optimized SVE instructions with predicate feature.
> 3. Some more SVE assemblers (and tests) used by the codegen part.
> 
> Note: VectorMask<E\> is still represented in vector register, a further improvement to map mask to predicate register is under development at https://github.com/openjdk/panama-vector/tree/vectorIntrinsics+mask
> 
> 
> Test: tier1-3 with vector api test cases passed on 512-bit SVE hardware with MaxVectorSize=16/32/64.

Ningsheng Jian has updated the pull request incrementally with one additional commit since the last revision:

  Add missing part

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Changes:
  - all: https://git.openjdk.java.net/jdk/pull/4122/files
  - new: https://git.openjdk.java.net/jdk/pull/4122/files/24100773..c444dc5a

Webrevs:
 - full: https://webrevs.openjdk.java.net/?repo=jdk&pr=4122&range=03
 - incr: https://webrevs.openjdk.java.net/?repo=jdk&pr=4122&range=02-03

  Stats: 129 lines in 2 files changed: 0 ins; 14 del; 115 mod
  Patch: https://git.openjdk.java.net/jdk/pull/4122.diff
  Fetch: git fetch https://git.openjdk.java.net/jdk pull/4122/head:pull/4122

PR: https://git.openjdk.java.net/jdk/pull/4122