RFR: 8259822: [PPC64] Support the prefixed instruction format added in POWER10 [v7]

[Corey Ashford]

On Wed, 24 Mar 2021 17:19:03 GMT, Kazunori Ogata <ogatak at openjdk.org> wrote:

>> The POWER10 processor, which implements Power ISA 3.1 [1], supports new instruction formats where an instruction takes two 32bit words.  The first word is called prefix, and the instructions with prefix are called prefixed instructions.  With more bits in opcode and operand fields, POWER10 supports larger immediate value in an operand, as well as many new instructions.
>> 
>> This is the first changes to handle prefixed instructions, and this adds support of prefixed addi (= paddi) instruction as an example of prefix usage.  paddi accepts 34bit immediate value, while original addi accepts 16bit value.
>> 
>> [1] https://ibm.ent.box.com/s/hhjfw0x0lrbtyzmiaffnbxh2fuo0fog0
>
> Kazunori Ogata has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Remove unused code and resolve merge conflict

No functional comments.  Just some minor grammar things.

src/hotspot/cpu/ppc/ppc.ad line 1162:

> 1160: int loadConI32Node::compute_padding(int current_offset) const {
> 1161:   assert(PowerArchitecturePPC64 >= 10 && (CodeEntryAlignment & 63) == 0,
> 1162:          "Code buffer must be aligned to a multiple of 64 byte");

... multiple of 64 bytes  (plural)

src/hotspot/cpu/ppc/ppc.ad line 1171:

> 1169: int loadConL34Node::compute_padding(int current_offset) const {
> 1170:   assert(PowerArchitecturePPC64 >= 10 && (CodeEntryAlignment & 63) == 0,
> 1171:          "Code buffer must be aligned to a multiple of 64 byte");

.. bytes

src/hotspot/cpu/ppc/ppc.ad line 1180:

> 1178: int addI_reg_imm32Node::compute_padding(int current_offset) const {
> 1179:   assert(PowerArchitecturePPC64 >= 10 && (CodeEntryAlignment & 63) == 0,
> 1180:          "Code buffer must be aligned to a multiple of 64 byte");

... bytes

src/hotspot/cpu/ppc/ppc.ad line 1189:

> 1187: int addL_reg_imm34Node::compute_padding(int current_offset) const {
> 1188:   assert(PowerArchitecturePPC64 >= 10 && (CodeEntryAlignment & 63) == 0,
> 1189:          "Code buffer must be aligned to a multiple of 64 byte");

... bytes

src/hotspot/cpu/ppc/ppc.ad line 1198:

> 1196: int addP_reg_imm34Node::compute_padding(int current_offset) const {
> 1197:   assert(PowerArchitecturePPC64 >= 10 && (CodeEntryAlignment & 63) == 0,
> 1198:          "Code buffer must be aligned to a multiple of 64 byte");

... bytes.

Since this string is used so many times, I almost feel like it ought to be factored out.

src/hotspot/cpu/ppc/ppc.ad line 1207:

> 1205: int cmprb_Whitespace_reg_reg_prefixedNode::compute_padding(int current_offset) const {
> 1206:   assert(PowerArchitecturePPC64 >= 10 && (CodeEntryAlignment & 63) == 0,
> 1207:          "Code buffer must be aligned to a multiple of 64 byte");

... bytes

src/hotspot/cpu/ppc/ppc.ad line 5895:

> 5893:   match(Set dst src);
> 5894:   // This macro is valid only in Power 10 and up, but adding the following predicate here
> 5895:   // caused build error. So we comment it out for now.

small grammar issue:

// caused **a** build error **, so** we comment it out for now.

src/hotspot/cpu/ppc/ppc.ad line 5984:

> 5982:   match(Set dst src);
> 5983:   // This macro is valid only in Power 10 and up, but adding the following predicate here
> 5984:   // caused build error. So we comment it out for now.

// caused **a** build error **, so** we comment it out for now.

-------------

Changes requested by cashford (Author).

PR: https://git.openjdk.java.net/jdk/pull/2095