RFR: 8276108: Wrong instruction generation in aarch64 backend

[Patric Hedlin]

C1 code generation on AArch64 may produce bad LDR/STR immediate offset instructions when the actual operand (datum) size is unknown. This change will alter the code generated for the problematic immediate offset to use the register offset version (requiring additional instructions).

Contributed by Nick Gasson.

Added assert in Address::encode() to emphasise the use of a valid immediate (in base_plus_offset).

Added clarifying comment to Address::offset_ok_for_immed() emphasising favouring of the scaled unsigned 12-bit encoding for aligned offsets.

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Commit messages:
 - Replacing worst case assumption with proper(?) type size calc.
 - 8276108: Wrong instruction generation in aarch64 backend

Changes: https://git.openjdk.java.net/jdk/pull/6212/files
 Webrev: https://webrevs.openjdk.java.net/?repo=jdk&pr=6212&range=00
  Issue: https://bugs.openjdk.java.net/browse/JDK-8276108
  Stats: 30 lines in 3 files changed: 13 ins; 1 del; 16 mod
  Patch: https://git.openjdk.java.net/jdk/pull/6212.diff
  Fetch: git fetch https://git.openjdk.java.net/jdk pull/6212/head:pull/6212

PR: https://git.openjdk.java.net/jdk/pull/6212