RFR: 8277239: SIGSEGV in vrshift_reg_maskedNode::emit

[Dean Long]

On Wed, 17 Nov 2021 13:44:51 GMT, Jatin Bhateja <jbhateja at openjdk.org> wrote:

> Currently instruction selector differentiates between the two kinds of vector shift operations i.e. one with vector shift count and other with scalar shift count passed though LShiftCntV/RShiftCntV nodes by looking at the ideal opcode of shift count node.
> 
> A more robust scheme is to set a flag over vector shift node if it has variable vector shift count and replace the opcode based check with flag based check in various shift instruction selection patterns.

Changes requested by dlong (Reviewer).

src/hotspot/share/opto/vectorIntrinsics.cpp line 526:

> 524:   } else {
> 525:     const TypeVect* vt = TypeVect::make(elem_bt, num_elem, is_vector_mask(vbox_klass));
> 526:     bool is_var_shift = VectorNode::is_shift_opcode(opc);

how about moving this down to where it is used?

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PR: https://git.openjdk.java.net/jdk/pull/6431