RFR: 8276108: Wrong instruction generation in aarch64 backend

[Andrew Haley]

On Tue, 2 Nov 2021 14:02:48 GMT, Patric Hedlin <phedlin at openjdk.org> wrote:

> C1 code generation on AArch64 may produce bad LDR/STR immediate offset instructions when the actual operand (datum) size is unknown. This change will alter the code generated for the problematic immediate offset to use the register offset version (requiring additional instructions).
> 
> Contributed by Nick Gasson.
> 
> Added assert in Address::encode() to emphasise the use of a valid immediate (in base_plus_offset).
> 
> Added clarifying comment to Address::offset_ok_for_immed() emphasising favouring of the scaled unsigned 12-bit encoding for aligned offsets.

I think this patch is too complicated.

I suggest:

--- a/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp
+++ b/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp
@@ -191,12 +191,10 @@ Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
       }
   } else  {
     intptr_t addr_offset = intptr_t(addr->disp());
-    if (Address::offset_ok_for_immed(addr_offset, addr->scale()))
-      return Address(base, addr_offset, Address::lsl(addr->scale()));
-    else {
-      __ mov(tmp, addr_offset);
-      return Address(base, tmp, Address::lsl(addr->scale()));
-    }
+    Address result(base, addr_offset, Address::lsl(addr->scale()));
+    // NOTE: Does not handle any 16 byte vector access.
+    const uint type_size = type2aelembytes(addr->type(), true);
+    return __ legitimize_address(result, type_size, tmp);
   }
   return Address();
 }

-------------

PR: https://git.openjdk.java.net/jdk/pull/6212