RFR: 8267356: AArch64: Vector API SVE codegen support [v7]

[Ningsheng Jian]

On Wed, 22 Sep 2021 03:17:47 GMT, Nick Gasson <ngasson at openjdk.org> wrote:

>> Ningsheng Jian has updated the pull request with a new target base due to a merge or a rebase. The pull request now contains six commits:
>> 
>>  - Merge with master
>>  - Merge with master
>>  - More comments from Andrew.
>>  - Add missing part
>>  - Address Andrew's comments
>>  - 8267356: AArch64: Vector API SVE codegen support
>>    
>>    This is the integration of current SVE work done in
>>    panama-vector/vectorIntrinscs, which includes:
>>    
>>    1. Code generation for Vector API c2 IR nodes with SVE.
>>    2. Non-max vector size support with SVE, e.g. using *128Vector APIs on
>>       256-bit SVE environment could also generate optimized SVE
>>       instructions with predicate feature.
>>    3. Some more SVE assemblers (and tests) used by the codegen part.
>>    
>>    Note: VectorMask<E> is still represented in vector register, a further
>>    improvement to map mask to predicate register is under development at
>>    https://github.com/openjdk/panama-vector/tree/vectorIntrinsics+mask
>>    
>>    Test: tier1-3 with vector api test cases passed on 512-bit SVE hardware
>>    with MaxVectorSize=16/32/64.
>
> Marked as reviewed by ngasson (Reviewer).

Thank you @nick-arm for the review!

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PR: https://git.openjdk.java.net/jdk/pull/4122