RFR: 8290154: [JVMCI] partially implement JVMCI for RISC-V [v5]

[Fei Yang]

On Wed, 27 Jul 2022 11:25:22 GMT, Sacha Coppey <duke at openjdk.org> wrote:

>> This patch adds a partial JVMCI implementation for RISC-V, to allow using the GraalVM Native Image RISC-V LLVM backend, which does not use JVMCI for code emission.
>> It creates the jdk.vm.ci.riscv64 and jdk.vm.ci.hotspot.riscv64 packages, as well as implements a part of jvmciCodeInstaller_riscv64.cpp. To check for correctness, it enables JVMCI code installation tests on RISC-V. More testing is performed in Native Image.
>
> Sacha Coppey has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Add space in switch

I have some comments.

src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.riscv64/src/jdk/vm/ci/riscv64/RISCV64Kind.java line 54:

> 52:     V256_QWORD(32, QWORD),
> 53:     V256_SINGLE(32, SINGLE),
> 54:     V256_DOUBLE(32, DOUBLE);

I see some vector types are added here. Could you please explain the design here?
Please note that RISC-V Vector extension (RVV) uses variable length vectors which in this sense is similar to AArch64's SVE. The actual vector length depends on the hardware implementation and could be determind by reading from the corresponding CSR special register at runtime. I am not sure how JVMCI is supposed to support this.

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PR: https://git.openjdk.org/jdk/pull/9587