RFR: 8290082: [PPC64] ZGC C2 load barrier stub needs to preserve vector registers [v2]

[Richard Reingruber]

On Mon, 11 Jul 2022 15:36:35 GMT, Martin Doerr <mdoerr at openjdk.org> wrote:

>> Preserve volatile vector registers in ZGC C2 load barrier stub.
>
> Martin Doerr has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Avoid using more than the volatile program storage (288 Bytes) on stack below the SP.

src/hotspot/cpu/ppc/gc/z/zBarrierSetAssembler_ppc.cpp line 486:

> 484:         assert(SuperwordUseVSX, "or should not reach here");
> 485:         VectorSRegister vs_reg = vm_reg->as_VectorSRegister();
> 486:         if (vs_reg->encoding() >= VSR32->encoding() && vs_reg->encoding() <= VSR51->encoding()) {

Why VSR32 as lower bound? I read in ppc.ad

1st 32 VSRs are aliases for the FPRs wich are already defined above.

Could you please help and explain what this means?

Why VSR51 as upper bound?

I'd suggest to update the comment in register_ppc.hpp and explain the vector scalar registers.
What is the difference between vector and vector scalar registers?

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PR: https://git.openjdk.org/jdk/pull/9453