RFR: 8283232: x86: Improve vector broadcast operations [v12]

[Jatin Bhateja]

On Fri, 29 Jul 2022 13:39:31 GMT, Quan Anh Mai <duke at openjdk.org> wrote:

>> src/hotspot/cpu/x86/x86.ad line 4159:
>> 
>>> 4157: 
>>> 4158: instruct vReplS_reg(vec dst, rRegI src) %{
>>> 4159:   predicate(UseAVX >= 2);
>> 
>> Can be folded with below pattern, by pushing predicate into encoding block.
>
> Aligning the predicate of the reg and the mem version allows the adlc parser to recognise their relationship and during register allocation can substitute a reg operation with a spilt operand with its corresponding mem node. You can see in the generated code the reg node has specific methods such as `cisc_operand` and `cisc_version`

May be a misplaced comment, what I meant was to collapse patterns if number and register class of operands comply.

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PR: https://git.openjdk.org/jdk/pull/7832