RFR: 8283307: Vectorize unsigned shift right on signed subword types [v3]

[Sandhya Viswanathan]

On Wed, 1 Jun 2022 02:13:47 GMT, Pengfei Li <pli at openjdk.org> wrote:

>> test/hotspot/jtreg/compiler/c2/irTests/TestVectorizeURShiftSubword.java line 36:
>> 
>>> 34:  * @key randomness
>>> 35:  * @summary Auto-vectorization enhancement for unsigned shift right on signed subword types
>>> 36:  * @requires os.arch=="amd64" | os.arch=="x86_64" | os.arch=="aarch64"
>> 
>> This IR test for vectorizable check looks good on AArch64. But AFAIK, some operations cannot be vectorized on old x86 CPUs with AVX=1. Could you add something like `(os.simpleArch == "x64" & vm.cpu.features ~= ".*avx2.*")` to check the CPU feature?
>
> @merykitty @sviswa7 Could you help confirm if byte/short shift operations are vectorizable with all AVX versions of x86?

@pfustc They are available either directly or through a series of instructions for majority of the architectures. All implemented in x86.ad. The match_rule_supported and match_rule_supported_vector will appropriately return true/false.

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PR: https://git.openjdk.java.net/jdk/pull/7979