RFR: 8283694: Improve bit manipulation and boolean to integer conversion operations on x86_64 [v7]

Fri Jun 3 15:45:37 UTC 2022

On Fri, 3 Jun 2022 15:37:07 GMT, Dean Long <dlong at openjdk.org> wrote:

>> Yes you are right, the change reduces 1 cycle of latency but may require another register so I reverted it. Thanks a lot.
>
> Does this pattern give any improvement?
> 
> testl $src, $src
> movl $dst, 0
> setnz $dst

`movl r, 0` is not a zero idiom, so a partial register write later of `setcc` would lead to register stall when the value is read.

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PR: https://git.openjdk.java.net/jdk/pull/7968