RFR: 8282555: Missing memory edge when spilling MoveF2I, MoveD2L etc

[Jatin Bhateja]

On Tue, 29 Mar 2022 10:37:21 GMT, Emanuel Peter <duke at openjdk.java.net> wrote:

> Do you know why we add the memory edge before the inputs in the other cases? If I use `add_prec` then that adds the memory edge after the inputs, correct?

Currently memory edges are being added for instructions which directly access memory,  ADLC enforces this by scanning through Ideal nodes of a matcher pattern in top-down manner. 
Almost all the machine nodes decorated with **Flag_is_cisc_alternate** flag access Load/Store IR in their selection patterns. Only exceptions[1][2][3] as you pointed out are the ones which perform load/store from stack locations. Thus all I am suggesting is for all such cases without doing many changes we can add the DEF_Spill precedence edge which gets added after all the inputs but will still constrain the scheduling order. 

Thus an instructions which has a CISC alternate but lacks memory_operand can be handled by adding a prescience edge.

 [1] MoveF2I_stack_regNode() {  _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); }
 [2] MoveI2F_stack_regNode() {  _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); }
 [3] MoveD2L_stack_regNode() {  _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); }

-------------

PR: https://git.openjdk.java.net/jdk/pull/7889