RFR: 8294194: [AArch64] Create intrinsics compress and expand [v2]

[Stuart Monteith]

On Tue, 1 Nov 2022 11:35:09 GMT, Andrew Haley <aph at openjdk.org> wrote:

>> I'm not sure exactly what you are asking about here. However, if it is about the Op_CacheWB* checks then the answer is no. These are memory flush operations that are used by the code that syncs writes to persistent memory (NVRam) mapped buffers.
>
> I'm talking about the SVE intrinsics.

@theRealAph  just means the cases for op_ExpandBits/op_CompressBits.
aarch64_sve.ad was merged with aarch64_neon.ad into aarch64_vector.ad, but while I'm using SVE instructions, I'm not using SVE types. match_rule_supported_vector isn't called by the scalar compiler code for intrinsics, and so we'd be deviating further from the common code. I'm reluctant to move the rules into aarch64_vector.ad file, as that would separate it from the match_rule_supported code that enables it - placing it among vector code doesn't really match the intent behind the code using vector instructions to perform scalar operations.

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PR: https://git.openjdk.org/jdk/pull/10537