RFR: 8296136: Use correct register in aarch64_enc_fast_unlock()

[Roman Kennke]

On Tue, 1 Nov 2022 06:52:31 GMT, Fei Yang <fyang at openjdk.org> wrote:

> Could you please also incorporate following fix for RISC-V at the same time? I see it inherits the same similar issue here. This has passed tier1 test on HiFive Unmatched board. Thanks.
> 
> ```
> diff --git a/src/hotspot/cpu/riscv/riscv.ad b/src/hotspot/cpu/riscv/riscv.ad
> index 75612ef7508..abe0f609a62 100644
> --- a/src/hotspot/cpu/riscv/riscv.ad
> +++ b/src/hotspot/cpu/riscv/riscv.ad
> @@ -2474,7 +2474,7 @@ encode %{
> 
>      // Handle existing monitor.
>      __ ld(tmp, Address(oop, oopDesc::mark_offset_in_bytes()));
> -    __ andi(t0, disp_hdr, markWord::monitor_value);
> +    __ andi(t0, tmp, markWord::monitor_value);
>      __ bnez(t0, object_has_monitor);
> 
>      if (!UseHeavyMonitors) {
> ```

I pushed the proposed fix for RISC-V. Could you please give it a quick build and smoke test, and approve the PR? Then I'd integrate it. Thanks!

-------------

PR: https://git.openjdk.org/jdk/pull/10921