RFR: 8295968: RISC-V: Rename some assembler intrinsic functions for RVV 1.0. [v3]

[Fei Yang]

On Thu, 27 Oct 2022 08:39:53 GMT, Dingli Zhang <dzhang at openjdk.org> wrote:

>> Hi,
>> 
>> Some instructions previously had old assembler notation, but were renamed in RVV1.0 to be consistent with scalar instructions, such as `vpopc_m->vcpop_m`[1] , `vfredsum_vs->vfredusum_vs`[2], `vmornot_mm->vmorn_mm/vmandnot_mm->vmandn_mm`[3], `vle1_v->vlm_v/vse1_v->vsm_v`[4]. We'd better keep the name the same as the new assembler mnemonics.
>> 
>> The instruction `vl1r.v` in rvv0.9[5] is the same logic as `vl1re8.v` in rvv1.0[6], while in rvv1.0 it becomes a pseudoinstruction which is equal to `vl1re8.v`.
>> 
>> By the way, we can find all the rvv aliases here[7].
>> 
>> Please take a look and have some reviews. Thanks a lot.
>> 
>> 
>> [1] https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc#152-vector-count-population-in-mask-vcpopm
>> [2] https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc#143-vector-single-width-floating-point-reduction-instructions
>> [3] https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc#151-vector-mask-register-logical-instructions
>> [4] https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc#74-vector-unit-stride-instructions
>> [5] https://github.com/riscv/riscv-v-spec/blob/0.9/v-spec.adoc#79-vector-loadstore-whole-register-instructions
>> [6] https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc#79-vector-loadstore-whole-register-instructions
>> [7] https://github.com/riscv/riscv-opcodes/blob/master/rv_v_aliases
>> 
>> ## Testing:
>> 
>> - hotspot and jdk tier1 on unmatched board without new failures
>
> Dingli Zhang has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Fix alignment

Looks good. I think it should be easy to add those instruction aliases in macro-assembler when they are really needed some day.

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Marked as reviewed by fyang (Reviewer).

PR: https://git.openjdk.org/jdk/pull/10878