RFR: 8295261: RISC-V: Support ReductionV instructions for Vector API

[Yadong Wang]

On Fri, 4 Nov 2022 06:21:17 GMT, Gui Cao <gcao at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/riscv_v.ad line 814:
>> 
>>> 812:             "vmv.x.s  $dst, $tmp" %}
>>> 813:   ins_encode %{
>>> 814:     __ vsetvli(t0, x0, Assembler::e64);
>> 
>> Only the element basic type of the two code segments is different. Could you use Matcher::vector_element_basic_type() to simplify the code?
>
> @yadongw Hello, thanks for review. the current definition of AndReductionV node of riscv refers to the AndReductionV node of aarch64 and the AddReductionVI, AddReductionVL of riscv. The parameter types of the nodes here are different. At present, Matcher::vector_element_basic_type() should not be used to simplify the code.
> 
> For example, the AndReductionV node of aarch64 defines the parameter types as follows:
> 
> instruct reduce_andI_sve(iRegINoSp dst, iRegIorL2I isrc, vReg vsrc, vRegD tmp)
> 
> instruct reduce_andL_sve(iRegLNoSp dst, iRegL isrc, vReg vsrc, vRegD tmp)
> 
> 
> riscv's AddReductionVI, AddReductionVL node defines the parameter types as follows:
> 
> instruct reduce_addI(iRegINoSp dst, iRegIorL2I src1, vReg src2, vReg tmp)
> 
> instruct reduce_addL(iRegLNoSp dst, iRegL src1, vReg src2, vReg tmp)

Okay, that's fine.

-------------

PR: https://git.openjdk.org/jdk/pull/10691