RFR: 8294194: [AArch64] Create intrinsics compress and expand

[Andrew Dinn]

On Tue, 25 Oct 2022 03:09:15 GMT, Hao Sun <haosun at openjdk.org> wrote:

>> src/hotspot/cpu/aarch64/aarch64.ad line 16948:
>> 
>>> 16946: instruct compressBitsI_reg(iRegINoSp dst, iRegIorL2I src, iRegIorL2I mask,
>>> 16947:                            vRegF tdst, vRegF tsrc, vRegF tmask) %{
>>> 16948:   match(Set dst (CompressBits src mask));
>> 
>> I would suggest aligning the predicate with the conditions in Matcher::match_rule_supported(int opcode). 
>> Suggestion:
>> 
>> predicate(UseSVE > 1 && VM_Version::supports_svebitperm());
>> match(Set dst (CompressBits src mask));
>
> I suppose the predicate-stmt is not needed here, since the check has already been done in `match_rule_supported()` helper.

That's a good point. x86 rules all appear to omit any checks that appear in `match_rule_supported` (in most cases they have no predicate, in others they have a predicate that includes a further sub-constraint).

For AArch64 the predicate test in `match_rule_supported` is omitted for `OP_OnSpinWait` but retained for `Op_CacheWB`, `CacheWBPreSync` and `CacheWBPostSync`. We should probably make this consistent by removing the repeat predicates for those last three cases as well.

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PR: https://git.openjdk.org/jdk/pull/10537