RFR: 8290917: x86: Memory-operand arithmetic instructions have too low costs [v5]

[Jatin Bhateja]

On Thu, 15 Sep 2022 09:17:07 GMT, Quan Anh Mai <duke at openjdk.org> wrote:

>> The pattern `AddI (LoadI mem) imm` should be matched by a load followed by an add with constant, instead, it is currently matched as a constant load followed by an add with memory. The reason is that the cost of `addI_rReg_mem` is too low, this patch fixes this by increasing the cost of this fused instruction.
>> 
>> Testing: Manually run the test case in the JBS and look at the compiled code.
>> 
>> I also do some small clean-ups in x86_64.ad:
>> 
>> - The `mulHiL` rules have unnecessary constraints on the input registers, these can be removed. The `no_rax_RegL` operand as a consequence can also be removed.
>> - The rules involving long division by a constant can be removed because it has been covered by the optimiser during idealisation.
>> - The pattern `SubI src imm` and the likes never match because they are converted to `AddI src -imm` by the optimiser. As a result, these rules can be removed
>> - The rules involving shifting the argument by 1 are covered by and exactly the same as the corresponding rules of shifting by an immediate. As a result, they can be removed.
>> - Some rules involving and-ing with a bit mask have unnecessary constraints on the target register.
>> 
>> Please kindly review, thank you very much.
>
> Quan Anh Mai has updated the pull request incrementally with one additional commit since the last revision:
> 
>   divL_10

src/hotspot/cpu/x86/x86_64.ad line 9764:

> 9762: 
> 9763: // And Register with Immediate 255
> 9764: instruct andI_rReg_imm255(rRegI dst, rRegI src, immI_255 mask)

Looks good, will save additional move emittion for two address instruction by RA, generally which will be sweeped out if both src and dst registers have same encodings, else may result into spill in case of high register pressure blocks.

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PR: https://git.openjdk.org/jdk/pull/9791