RFR: 8302908: RISC-V: Support masked vector arithmetic instructions for Vector API [v13]

[Dingli Zhang]

On Fri, 7 Apr 2023 02:43:52 GMT, Gui Cao <gcao at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/riscv_v.ad line 2457:
>> 
>>> 2455: %}
>>> 2456: 
>>> 2457: instruct vmask_gen_sub(vRegMask dst, iRegL src1, iRegL src2) %{
>> 
>> (One more comment) This rule looks redundant for RISC-V. We have this on AArch64 because we can match the nodes to SVE `whileXX` to save a `sub` instruction. But it looks no instruction is saved according to your RISC-V implementation. Actually, `SubL` and `VectorMaskGen` can be matched separately without this.
>
> Hi, thanks for the review. this node is really not needed here,`SubL` and `VectorMaskGen` can be matched separately without this. 
> After removing this node, `SubL` and `VectorMaskGen` can be matched separately, The compilation log is as follows:
> 
> 148     B11: #	out( B21 B12 ) <- in( B9 )  Freq: 0.00838607
> 148     addw  R7, R29, zr	#@convI2L_reg_reg
> 14c     addw  R28, R28, zr	#@convI2L_reg_reg
> 150     sub  R7, R7, R28	#@subL_reg_reg
> 154     vmask_gen_L V0, R7
> 15c     vstoremask V5, V0
> 168     ld  R30, [R23, #264]	# ptr, #@loadP
> 16c     ld  R7, [R23, #280]	# ptr, #@loadP
> 170     addi  R28, R30, #48	# ptr, #@addP_reg_imm
> 174     bgeu  R28, R7, B21	#@cmpP_branch  P=0.000100 C=-1.000000

Thanks and fixed.
The 75 tests under `test/jdk/jdk/incubator/vector` passed as usual.

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PR Review Comment: https://git.openjdk.org/jdk/pull/12682#discussion_r1160660600