RFR: 8305728: RISC-V: Use bexti instruction to do single-bit testing

[Fei Yang]

On Thu, 6 Apr 2023 00:52:15 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

> Current RISC-V port tests bit masks with `andi` instruction. But for those mask values not in the range of `simm12` (`andi`
> only accepts sign-extended 12-bit immediate [1]), we need an extra temp register (`t0` as default for `andi`) to store the mask value [2].
> Since we now support Zbs extension of Bit-Manipulation, we have a more convenient way to test power-of-two bit
> masks with the single instruction `bexti` [3] without any temp register.
> 
> 1. https://github.com/riscv/riscv-isa-manual/blob/f6b8d5c7d2dcd935b48689a337c8f5bc2be4b5e5/src/rv32.tex#L519-L521
> 2. https://github.com/openjdk/jdk/blob/ce6e7461dc5ac56459a79e75d5de76929d1be0a3/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp#L1852-L1860
> 3. https://github.com/riscv/riscv-bitmanip/blob/main/bitmanip/insns/bexti.adoc
> 
> Testing:
> - [x] `hotspot_tier1`, `jdk_tier1` on QEMU-User w/ and w/o `UseZbs` (release build)
> - [x] tier1 tests on unmatched board w/o `UseZbs` (release build)

Looks good. Thanks.

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Marked as reviewed by fyang (Reviewer).

PR Review: https://git.openjdk.org/jdk/pull/13368#pullrequestreview-1377039293